floating-point adder
英 [ˈfləʊtɪŋ pɔɪnt ˈædə(r)]
美 [ˈfloʊtɪŋ pɔɪnt ˈædər]
浮点加法器
双语例句
- Floating-point adder As she watched him eat, there was an expression of great tenderness in her face.
当她望着他吃东西的时候一种异常温柔的神色浮上了她的脸庞。 - UV Spectrophotometric Determination of Trace Amounts of Doxycycline in Water with Separation and Enrichment by Gas Floatation floating-point adder
气浮浮选分离富集-紫外分光光度法测定水中痕量强力霉素 - The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。 - Through the structure and logical designing, we get a high-speed and effective LOD circuit, which applied in floating-point adder.
我们从LOD的组成结构和逻辑两个方面进行设计，实现了一种快速、高效的LOD电路。 - The FPGA Implementation of the Triple Data-path Floating-point Adder
三数据通道浮点加法器的FPGA实现 - The pipelining technique of 32 bit floating-point adder/ subtracter and multiplier is introduced in detail, which can enhance the performance of the FFT processor.
详细讨论了32位浮点加法器/减法器、乘法器的分级流水技术，提高了系统性能。 - A Design of LOD for DSP Floating-Point Adder
DSP芯片中浮点加法器LOD电路的设计 - High-Speed Floating-point Adder is a critical part in the coprocessor, which is attached to the computing basis of floating-point instructions.
浮点加法器是协处理器的核心运算部件，是实现浮点指令各种运算的基础，其设计优化是提高浮点运算速度和精度的关键途径。 - A multiple-input floating-point adder is usually composed of several double-input floating-point adders, and it is inevitable to increase the logic resources and processing latency, which makes it harder and harder to meet the requirements of high-speed digital signal processing.
传统的多输入浮点加法运算是通过级联二输入浮点加法器来实现的，这种结构不可避免地使运算时延和所需逻辑资源成倍增加，从而越来越难以满足需要进行高速数字信号处理的需求。 - The main research area is the structure optimization of floating-point adder, which is intent to minimize the delay of floating-point addition and optimize the circuit structure.
主要研究方向是优化浮点加法器结构，减小浮点加法运算的延迟，优化电路结构。 - Sub-modules including the floating-point adder, floating-point multiplier, floating-point divider, trigonometric function device.
子模块包括浮点加法器、浮点乘法器、浮点除法器和三角函数器。 - Computing units includes a custom 18-bit floating-point adder, subtraction, multiplier and divider.
基本运算单元包括18位自定义的的浮点数加法器、减法器、乘法器和除法器。 - The data and conclusions prove that these designs are better than the original ones; the floating-point adder is really optimized.
实验证明这些设计的性能都比原有设计有所提高，达到了优化浮点加法器的目的。